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This paper describes a high voltage process using 0.8 p technology for mixed signal applications. The technology allows the integration of high side 20, 30 and 50-V n-type LDMOS transistors and 50V p-type LDMOS transistor along with dense logic 1 analog 5V-CMOS and complementary low and high voltage bipolar transistors. Extended drain NMOS and PMOS transistors (ENMOS-EPMOS) whose safe operating areas exceed 50V were also implemented. This technology is ideal for intelligent power application.

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