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Other books in the series: Adaptive Filters: Structures, Algorithms, and Applications. M.L. Honig and D.G. Messerschmitt. ISBN 0-89838-163-0. Introduction to VLSI Silicon Devices: Physics, Technology and Characterization. B. El-Kareh and R.J. Bombard. ISBN 0-89838-210-6. Latchup in CMOS Technology: The Problem and Its Cure. R.R. Troutman. ISBN 0-89838-215-7. Digital CMOS Circuit Design. M. Annaratone. ISBN 0-89838-224-6. The Bounding Approach to VLSI Circuit Simulation. C.A. Zukowski. ISBN 0-89838-176-2. Multi-Level Simulation for VLSI Design. D.D. Hill and D.R. Coelho. ISBN 0-89838-184-3. Relaxation Techniques for the Simulation of VLSI Circuits. J. White and A. Sangiovanni-Vincentelli. ISBN 0-89838-186-X. VLSI CAD Tools and Applications. W. Fichtner and M. Morf, Editors. ISBN 0-89838-193-2. A VLSI Architecture for Concurrent Data Structures. W.J. Dally. ISBN 0-89838-235-1. Yield Simulation for Integrated Circuits. D.M.H. Walker. ISBN 0-89838-244-0. . Switch-Level Timing Simulation of MOS VLSI Circuits. V.B. Rao, D.V. Overhauser, T.N. Trick, LN. Hajj. ISBN 0-89838-302-1. VLSI for Artificial Intelligence. J.G. Delgado-Frias, W.R. Moore (Editors). ISBN 0-7923-9000-8. Wafer Level Integrated Systems: Implementation Issues. S.K. Tewksbury. ISBN 0-7923-9006-7. The Annealing Algorithm. R.H.J .M. Otten & L.P.P.P. van Ginneken. ISBN 0-7923-9022-9. VHDL: Hardware Description and Design. R. Lipsett, C. Schaefer and C. Ussery. ISBN 0-7923-9030-X. The VHDL Handbook. D. Coelho. ISBN 0-7923-9031-8. Unified Methods for VLSI Simulation and Test Generation. K.T. Cheng and V.D. Agrawal. ISBN 0-7923-9025-3. ASIC System Design with VHDL: A Paradigm. S.S. Leung and M.A. Shanblatt. ISBN 0-7923-9032-6. BiCMOS Technology and Applications. A.R. Alvarez (Editor). ISBN 0-7923-9033-4. Analog VLSI Implementation of Neural Systems. C. Mead and M. Ismail (Editors). ISBN 0-7923-9040-7. The MIPS-X RISC Microprocessor. P. Chow. ISBN 0-7923-9045-8. Nonlinear Digital Filters: Principles and Applications. I. Pitas and A.N. Venetsanopoulos. ISBN 0-7923-9049-0. Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench.

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