The architectural advancements in desktop computing have made embedded devices in real time applications to adopt multi core architectures. Constrained power availability but ever increasing performance requirements are the main reason for this migration. Failure to allocate tasks to specific cores would result in some tasks running while other tasks in other cores remaining idle. The efficiency of the entire system would decrease and the tasks with higher priority could cause bottlenecks. In this work, we propose a model which could analyze, split and allocate the tasks to cores. The results of the proposed model for a real time automobile application were observed to be effective on multi core architecture.

The architectural advancements in desktop computing have made embedded devices in real time applications to adopt multi core architectures. The main challenge in multi core programming is the process of communication between the different executing cores. Effectiveness of parallel programming in multi core architectures lies in method used for communication. Communication using shared cache is one of the popular approaches. This paper discusses in detail one of the novel methods of inter core communication.Correctness of the algorithm has been based on results obtained on a hard real time system.