In September 2003, America West Airlines implemented a new aircraft boarding strategy that reduces the airline’s average passenger boarding time by over two minutes, or approximately 20 percent, for full and nearly full flights. The strategy, developed by a team of Arizona State University and America West Airline’s personnel, is a hybrid between traditional back-to-front boarding and outside-inside boarding used by other airlines. Field observations, numerical results of analytical models, and simulation studies provided information that resulted in an improved aircraft-boarding strategy termed reverse pyramid. With the new boarding strategy, passengers still have personal seat assignments, but rather than boarding by rows from the back to the front of the airplane, they board in groups minimizing expected passenger interference in the airplane. The analytical, simulation, and implementation results obtained show that the method represents a significant improvement in terms of boarding time over traditional pure back-to-front, outside-inside boarding strategies.

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A summary of electrical and optical approaches to clock distribution within high-performance microprocessors is presented. System-level properties of intrachip electrical clock distribution networks corresponding to three microprocessor families are summarized. It is found that global clock interconnect performance and short-term jitter present the greatest challenges to the continued use of conventional clock distribution methodologies. An extrapolation of trends describing the percentage of clock period consumed by global skew and short-term jitter identifies the 32-nm technology generation of the 2002 International Technology Roadmap for Semiconductors (ITRS) as the first technology generation within which alternate methods of clock distribution may be warranted. Research efforts investigating interboard through intrachip optical clock distribution are also summarized. An optical distribution network compatible with high volume manufacturing in conjunction with a suitable means of providing optical-to-electrical signal conversion comprise the two fundamental challenges facing successful implementation of an optical clock distribution network. It is found that a global guided-wave distribution capable of efficient input and output coupling of optical power is required to meet the first challenge. The identification of a suitable means of optical-to-electrical conversion, however, remains an active topic of research.Index Terms-High performance, high-speed interconnect, optical, optoelectronic integrated circuits, system level, VLSI.

The lengths beyond which board-level optical waveguides are capable of transferring a larger number of bits per second than electrical interconnects are found for various technology generations. As technology scales from the 130-nm technology node to the 45-nm technology node, the partition length falls from 29 to 8.3 cm due to seven times larger driver-switching frequency and 40% finer waveguide pitches.

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