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Fast Fourier transform (FFT) is an efficient algorithm to calculate Discrete Fourier Transform (DFT) and its inverse. A wide variety of applications like Digital Signal processing and image processing rely heavily on it. The FFT computation is done by the FFT processors and its design is a key factor for the application. The proposed design implements a radix-4 FFT processor, which incorporates a low power commutator and a Butterfly structure without a multiplier. The parallel pipe lined architecture of the processor also has higher throughput with lowered power consumption.

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We demonstrate minimum energy operation using a robust approach to asynchronous logic design combined with the use of sleep transistors. The combined approach yields extremely low power and energy for a system operating in the subthreshold regime. This enables operation at voltages below those associated with the previously proposed minimum energy operating point (MEP) and therefore appreciably reduces the energy consumption compared to MEP. We also demonstrate that the robustness of our asynchronous system under Monte Carlo variations can actually yield significant additional power savings compared to a synchronous design. Keywords-sleep, asynchronous design, low power, leakage energy, dynamic energy, minimum energy point, subthreshold.