We consider basic algorithms and processing technologies for integrated circuit layout images. The images represented as a set of frames can regard as a dataflow and the processing are perfectly suited for parallel implementation. We propose a framework architecture for designing parallel systems of image dataflow processing. The framework uses the algorithm of a virtual associative network for increasing processing speed and system throughput during runtime.

Basic principles of reliable parallel computations are considered. The parallel program is represented as a graph computation schema, that executed by unreliable computing system with possible node faults. For organization and optimization of parallel processing a kind of multiagent architecture was used. The proposed solution uses the principles of runtime evolutionary optimization to increase performance characteristics.