The continuing demand for higher bandwidth in serial interconnects has pushed the symbol rate of differential lanes into the high-insertion-loss region of channels. Multi-level signaling such as differential has been used to mitigate the loss of electrical channels by lowering the signal spectrum. Such an approach suffers from lower SNR tolerance as well as higher susceptibility to crosstalk and ISI as compared to differential signaling (DS). Coded differential approaches have been reported [2] to mitigate ISI. Our approach is a generalization of DS in which ternary values are transmitted on an 8-wire bus. The set of transmitted values belongs to a code consisting of 256 code-words called the 8b8w-code (8-bits-on-8-wires) [3]. The specific correlations in the code-words of the 8b8w-code eliminate transmit common-mode and simultaneous switching output (SSO) noise and allow for detection via selfreferencing comparators (unlike PAM-4), which provides additional noise immunity. Compared to DS, the 8b8w-code offers twice the throughput at 50% of the line power. Compared to PAM-4, the code offers better SNR (3dB) at 38% of the line power with enhanced tolerance of ISI and lower crosstalk generation. The design and experimental verification of an 8b8w transceiver in 40nm CMOS is described. Transmission is achieved up to 12Gb/s per wire over 55cm of Rogers with up to 15dB loss.The code-words are a permutation of the vector [+1, +1, −1, −1, 0, 0, 0, 0] and have the property that the sum of the ternary signals transmitted on the bus is 0 and thus have a balanced common mode voltage. Both the encoder and decoder have a maximum logic depth of 3 and are implemented with standard cells. The gate count for single instance of 8b encoder and decoder operating at 2GHz each is 81 and 63 respectively. The total power consumption and area for 8 such encoders is 3mW and 2000μm 2 . The corresponding numbers for decoder are 4mW and 1330μm 2 . Figure 26.3.1 shows the architecture of the transmitter. The 8 wires of the output driver are terminated to a common point, which is connected to an external pin driven with a common node voltage (V cm , nominally V DD /2). A digital encoder block (8 instances of 8b encoder) transforms 64 bits of incoming data into two streams of coded signals that are serialized and drive the PMOS and NMOS devices in a switched current-mode driver. The '0'-level is driven passively with both devices turned-off. A replica-current circuit is used to bias the current sources, providing a mechanism to control the voltage swing at the output of the transmitter (V cm ± ΔV swing ). A 1-tap programmable post-cursor FIR is included.Any skew between the wires manifests itself as high-frequency common-mode noise at the receiver. Figure 26.3.2 shows the architecture of the 8b8w receiver. To allow realignment without signal distortion, the receiver front-end is designed to pass high-frequency common-mode signals. The CTLE (shown in Fig. 26.3.3) is a hybrid between a generalized differential pair and a common-source amplifier....