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The phosphosilicate glass (PSG), fabricated by tube furnace diffusion using a POCl 3 source, is widely used as a dopant source in the manufacturing of crystalline silicon solar cells. Although it has been a widely addressed research topic for a long time, there is still lack of a comprehensive understanding of aspects such as the growth, the chemical composition, possible phosphorus depletion, the resulting in-diffused phosphorus profiles, the gettering behavior in silicon, and finally the metal-contact formation. This paper addresses these different aspects simultaneously to further optimize process conditions for photovoltaic applications. To do so, a wide range of experimental data is used and combined with device and process simulations, leading to a more comprehensive interpretation. The results show that slight changes in the PSG process conditions can produce high-quality emitters. It is predicted that PSG processes at 860 C for 60 min in combination with an etch-back and laser doping from PSG layer results in high-quality emitters with a peak dopant density N peak ¼ 8.0 Â 10 18 cm À3 and a junction depth d j ¼ 0.4 lm, resulting in a sheet resistivity q sh ¼ 380 X/sq and a saturation current-density J 0 below 10 fA/cm 2 . With these properties, the POCl 3 process can compete with ion implantation or doped oxide approaches. Published by AIP Publishing. [http://dx.

1 Introduction The emitter of crystalline silicon solar cells is usually formed in mass production by flowing POCl 3 through a furnace, which creates a phosphorussilicate glass (PSG) layer at the surfaces of the p-type wafers, from where phosphorus diffuses into the silicon. Only very recently has the phosphorus concentration in the PSG layer been measured [1]. It is firstly substantially higher than the solubility of P in Si, and secondly it changes only slightly with POCl 3 flow or other process parameters such as temperature. In this paper, a consequence of these recent findings is identified: the high flow of P into Si causes a far larger amount of (extrinsic) Shockley-Read-Hall (SRH) recombination than (intrinsic) Auger recombination. This implies that todays emitters are not Auger limited, but are instead SRH limited, and explains the large discrepancies between measured and simulated saturation current densities, J 0e , observed persistently over the last two decades in industrially fabricated Si solar cells. This clarification correlates strongly with recent cell efficiency improvements by reducing inactive phosphorus

The performance of passivated emitter and rear (PERC) solar cells made of p-type Si wafers is often limited by recombination in the phosphorus-doped emitter. To overcome this limitation, a realistic PERC solar cell is simulated, whereby the conventional phosphorus-doped emitter is replaced by a thin, crystalline gallium phosphide (GaP) layer. The resulting GaP/Si PERC cell is compared to Si PERC cells, which have (i) a standard POCl3 diffused emitter, (ii) a solid-state diffused emitter, or (iii) a high efficiency ion-implanted emitter. The maximum efficiencies for these realistic PERC cells are between 20.5% and 21.2% for the phosphorus-doped emitters (i)–(iii), and up to 21.6% for the GaP emitter. The major advantage of this GaP hetero-emitter is a significantly reduced recombination loss, resulting in a higher Voc. This is so because the high valence band offset between GaP and Si acts as a nearly ideal minority carrier blocker. This effect is comparable to amorphous Si. However, the GaP layer can be contacted with metal fingers like crystalline Si, so no conductive oxide is necessary. Compared to the conventional PERC structure, the GaP/Si PERC cell requires a lower Si base doping density, which reduces the impact of the boron-oxygen complexes. Despite the lower base doping, fewer rear local contacts are necessary. This is so because the GaP emitter shows reduced recombination, leading to a higher minority electron density in the base and, in turn, to a higher base conductivity.

In this paper we present latest results in the development of a process for the fabrication of a selective emitter structure on mono- and multicrystalline silicon solar cells. The process is based on an approach that was first introduced by Zerga et al. [1]. We have chosen a wet chemical route for an emitter etch back where the areas of the wafer that are intended for emitter metallization are shielded from etching by a screen printable etch barrier. The etch barrier is later removed by wet chemical etching. The process has yielded a gain in open circuit voltage of more than 1% and a gain in short circuit current of more than 2%. The overall efficiency gain was more than 0.3%abs due to slightly lower fill factor of the cells