This paper presents an attractive approach for bandwidth extension of a four quadrant CMOS analog multiplier. The proposed approach is based on using dynamic threshold MOS transistor (DTMOS) which is an effective technique that achieves supply voltage reduction with a simultaneous increase in the overall transconductance of the MOS transistor. The proposed multiplier can operate at very high frequencies at low supply voltage of 0.6V without any distortion. The proposed approach increases the bandwidth of multiplier by 4.6GHz at unity gain. This multiplier is simulated at 180nm technology and has high gain in comparison to previous reported circuit.The proposed approach optimizes multiplier bandwidth and thus more suitable for high frequency and low voltage applications.

In this paper we report a low voltage differential amplifier based on self-cascode topology which is suitable for low voltage and high speed operation. A negative conductance is used that will cancel the positive output conductance of an amplifier .As a result the total equivalent output conductance is reduced and thereby the overall voltage gain of the amplifier is increased .Using this technique we have achieved an increment in gain by a factor of 1.45 times. In bulk CMOS technology the body of the transistor can be used as a fourth terminal to enhance the performance of low-voltage analog circuits. Modeling the body effect will increase the overall transconductance of the MOS transistor.The use of Dynamic Threshold technique will enhance the gainbandwidth product of the amplifier.The gain bandwidth product has increased by 52.63%.Also the DTMOS technique is compatible with the standard bulk CMOS technique and hence there is no requirement for the additional area. Simulations are carried out using 180nm CMOS technology at 1V to validate the proposed idea.