This paper presents an efficient pipeline architecture to perform gray-scale morphologic operations. The features of the architecture are 1) lower hardware cost, 2) faster operation time in processing an image. 3) lower data access times from the image memory, 4) shorter latency, 5) suitability for VLSI implementation, and 6 ) adaptability for N*N morphologic operations.

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The authors present a new classified dynamic partial search structure for the stochastic codebook of the FS1016 CELP coder to replace the fixed partial search for selecting the best excitation vector of the stochastic codebook. In the proposed scheme, the conventional one-stage stochastic codebook search is substituted with a two-stage dynamic method for reducing the computational complexity without degrading the voice quality. The establishment of this structure is based on two classifiers, one for the line spectrum pairs (LSP) of the input signals, and the other for the autocorrelation coefficients (AC) of the stochastic codebook search target. In addition, the stochastic codebook is classified into K subcodebooks, and with these two classifiers it is possible to determine dynamically which subcodebook needs to be searched. This method achieves a reduction in the search procedure by a factor of 2-8. The efficiency of these two classifiers is discussed and the comparison of the performance between the fixed partial search and the proposed technique is also addressed. 0 IEE, 1995 Paper 1688K (ES), first received 6th May and in revised form 16th

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In this paper, we present the efficient VLSI architecture for the stand-alone application of the speech recognition system. With the analysis of the computation complexity, me1 frequency cepstrum extraction and Bayesian neural network operations are the most time consuming computation tasks in the recognition algorithm. The specific recognition core to deal with them is proposed based on much algorithm improvement. The construction of the special logarithm look-up table saves the computation time and drastically reduces the memory size. Moreover, the cost efficient programmable architecture is designed for other non computationintensive operations. The best aspects of both programmable and application specific architectures including the performance, design complexity, and flexibility are incorporated in the proposed VLSI speech recognizer.