No abstract

Supervised memory systems maintain additional metadata for each memory address accessed by the program, to control and monitor accesses to the program data. Supervised systems find use in several applications including memory checking, synchronization, race detection, and transactional memory. Conventional memory instructions are replaced by supervised memory instructions (SMIs) which operate on both data and metadata atomically. Existing proposals for supervised memory systems assume sequential consistency. Recently, Bobba et al. [4] demonstrated the correctness issues (imprecise exceptions and metadata read reordering) in naively applying supervision to Total-Store-Order, and proposed two solutions -TSOall and TSOdata -for overcoming the correctness issues. TSOall solves correctness issues by forcing SMIs to perform in order, but performs similar to SC, since supervised writes cannot retire into the write-buffer. TSOdata, while allowing supervised writes to retire into the write-buffer, works correctly for only a subset of supervision schemes. In this paper we observe that correctness is ensured as long as SMIs read and process their metadata in order. We propose SuperCoP, a supervised memory system for relaxed memory models in which SMIs read and process metadata before retirement, while allowing data and metadata writes to retire into the write-buffer. Since SuperCoP separates metadata reads and their processing from the writes, we propose a simple mechanism -in the form of cache block level locking at the directory -to ensure atomicity. Our experimental results show that SuperCoP performs better than TSOall by 16.8%. SuperCoP also performs better than TSOdata by 6%, even though TSOdata is not general.

Fence placement is required to ensure legacy parallel programs operate correctly on relaxed architectures. The challenge is to place as few fences as possible without comprising correctness. By identifying necessary conditions for a read to be an acquire we improve upon the state of the art for legacy DRF programs by up to 2.64x.

Fence placement is required to ensure legacy parallel programs operate correctly on relaxed architectures. The challenge is to place as few fences as possible without comprising correctness. By identifying necessary conditions for a read to be an acquire we improve upon the state of the art for legacy DRF programs by up to 2.64x.

Fence placement is required to ensure legacy parallel programs operate correctly on relaxed architectures. The challenge is to place as few fences as possible without comprising correctness. By identifying necessary conditions for a read to be an acquire we improve upon the state of the art for legacy DRF programs by up to 2.64x.