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In this paper, a novel self reconfigurable task scheduler is proposed to accomplish the reconfiguration without a processor. To overcome the latencies introduced by the processor based solutions, this paper proposes a HDL based self reconfigurable task scheduler to command directly Internal Configuration Access Port (ICAP) interface on a Virtex II Pro. Xilinx Block RAM feature is used to store the partial bit streams, to speed up the reconfiguration rate. The scheduler has to take into account the reconfiguration overhead of each task, the area constraint of the target FPGA, and the precedence between the tasks.To minimize loading latency and to schedule the loading of a set of configurations the scheduler inherently makes use of prefetch technique. The design proposed in this paper uses a direct memory interface and a key feature of the scheduling technique developed in this paper is the removal of the need to separately incorporate a prefetch policy. In order to prove the efficacy of this approach, Multi Band Orthogonal Frequency Division Multiplexing Ultra Wideband (MB-OFDM UWB) Transmitter is reconfigured for different data rates.

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