In this paper we are proposing a new approach for tasks allocation in a massively parallel system using Finite Automata. On the basis of task flow model of finite automata., we find the turnaround time for a parallel system using finite automata as a directed acyclic graph in the second section of the paper we discuss regarding the finite automata and directed acyclic graph after that we change finite automata into DAG for massively parallel system. All the simulations are performing in Intel C++ parallel compiler and compare these results with several interesting scheduling algorithms and we get better turnaround time.

Single Electron Transistor is often referred to as a nanometer scale because it can be made very small and can detect the movement of individual electrons. However, the SET has a high input impedance, low voltage gain, and is sensitive to random background charges. The Transfer characteristics features of a SET are calculated by analyzing the different resistance of the tunnels and the tunneling capacitance. Tunneling method is considering a stochastic process, and the state master equation is solving to calculate the free energy change. There are some unusual variations that set the limit for parallel circuit parameters for proper operation. The SET can maintain its scalability and control the movement of individual electrons. In this paper, we have provided a comparative and simulated study of standard CMOS device, SET and hybrid circuits such as a switched capacitor filter.