No abstract

This paper aims to design the pipeline who is considered a set of related data processing elements in a series where the result of one element is the introduction of the next one, and it can be used to increase performance and speed at the same time, and we use it in computer systems or home appliances. Increasing the voltage in the pipeline increases the power. When the clock frequency increases to increase the performance of the pipeline, the power increases but at the same time the possibility of an error increases. System errors will lead to a wasted in energy consumption which in turn reduces system efficiency. The problem is how to reduce the power in the pipeline system without effecting the process speed or frequency so that we mention the same throughput with this power. We will deal with N bit full adder and study the effect of increasing these bits on both the time delay and the power consumption of the pipeline gate, and the results show that there is a direct relationship between the number of bits and the power. The razor circuit is used with the pipeline so that the errors that will occur in the pipeline will be detected and corrected within one clock cycle instead of wasting the time and energy on incorrect data, thus the power consumption will be reduced. By introducing a Fuzzy logic controller to the pipeline, it was possible to minimize the power consumption of the system by monitoring the number of bit errors and the consumed power. Also, we will make a comparison of the pipeline when using the controller and when not in use, and we will notice the effect of the controller in reducing the power consumption of the pipeline.