a [ b [ c [ d [ e [ j [ k [ o [ t [ The CDF experiment's Silicon Vertex Trigger is a system of 150 custom 9U VME boards that reconstructs axial tracks in the CDF silicon strip detector in a 15 µsec pipeline. SVT's 35 µm impact parameter resolution enables CDF's Level 2 trigger to distinguish primary and secondary particles, and hence to collect large samples of hadronic bottom and charm decays. We review some of SVT's key design features. Speed is achieved with custom VLSI pattern recognition, linearized track fitting, pipelining, and parallel processing. Testing and reliability are aided by built-in logic state analysis and test-data sourcing at each board's input and output, a common inter-board data link, and a universal "Merger" board for data fan-in/fan-out. Speed and adaptability are enhanced by use of modern FPGAs.

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The CDF Online Silicon Vertex Tracker recontructs 2-D tracks by linking hit positions measured by the Silicon Vertex Detector to the Central Outer Chamber tracks found by the eXtremely Fast Tracker. The system has been completely built and assembled and it is now being commissioned using the rst CDF run II data. The precision measurement of the track impact parameter will allow triggering on B hadron decay vertices and thus investigating important areas in the B sector, like CP violation and B s mixing. In this paper we brie y review the architecture and the tracking algorithms implemented in the SVT and we report on the performance of the system achieved in the early phase of CDF run II.

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