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Abstrclct --Future SOC devices will make extensive use of phase locked loops tu either generate Gigahertz clocks on-chip or to adjust the phase of data signals in high speed 1O.Links running at multiple Gigabits per seeoud. The high . . speedanalog nature of the circuitry requires a dedicated test strategy to obtain fault coverage particularly for parametric defects affecting jitter performauee. While traditional specification ' . oriented test methods require a complex setup of additional instrumentation, this paper describes a completely new model based approach using existing capture and compare equipment available with ATE. The methodology proposed in this paper performs a test by verifying the frequeney domain model of the phase regulation characteristic developed during the design phase of the circuit. The method scales in performance and accuracy with leading edge measurement equipment such as ATE and BERT.