This Paper focuses on the realization and implementation of an efficient logic design of a convolutional encoder and adaptive Viterbi decoder (AVD) called cryptosystem with a constraint length, K of 3 and a code rate (k/n) of 1/2 using field programmable gate array (FPGA) technology. The adaptive viterbi decoder with convolutional encoder is a powerful forward error correction technique. This technique is particularly suited to a channel where the transmitted data is corrupted by additive white Gaussian noise. Viterbi algorithm is a maximum-likelihood algorithm for decoding of convolutional codes and these codes have good correcting capability and perform well on every noisy channel. In this paper viterbi decoder is designed for faster decoding speed and less are routing area. The proposed system is realized using verilog HDL and simulation is done by using modelsim SE 6.4c and Xilinx is used for RTL Design.

In most practical applications, accurate results are unnecessary, hence approximate computation is being used. By using approximate computing the system performance metrics like area, power and speed can be improved. This paper proposes an approximate circuit that was developed by modifying the circuit architecture but not the circuit operation. We propose an approximate multiplier using these approximate circuits, which use AND-OR logic approximation, Wallace tree reduction, and 3:2 inexact additive designs for partial product generation and addition. In this paper, by taking an 8X8 bit multiplication as an example, we show the whole proposed concept. Also, the proposed multipliers will cause substantial improvements in terms of both area and delay. Compared to the conventional multipliers, the AWM1 achieves up to 35.577% reduction in area and 35.224% in delay. AWM2 has an area and delay reductions of up to 48.077% and 36.532% respectively. AWM3 has area savings of up to 48.077% and delay reductions of up to 46.633%. Finally, the AWM4 has area savings of up to 53.846% and delay reductions of up to 56.482%.

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