This work presents a novel low leakage SRAM architecture with always-retention and local wake-up. To tackle the large design margins in deep sub-micron technology nodes, it includes SNM monitoring and compensation circuitry to track variation across the memory array. This allows for operation close to the point of first failure. As proof of concept, a macro of 1Mbit is fabricated in 22nm FDSOI. Measurements show an active energy of 3.6 pJ/access at 6.6 MHz and a leakage power of 0.19 pW/cell, a reduction of 53.8% due to margin reduction.