We propose a new NAND programming scheme called the lazy reprogramming scheme (LazyRS) which divides a program operation into two stages, where the second stage is delayed until it is needed. LazyRS optimizes the program latency by skipping the second stage if it is not required. An idle interval before the second stage improves the flash reliability as well. To maximize the benefit of LazyRS, a LazyRS-aware FTL adjusts the length of an idle interval dynamically over changing workload characteristics. The experimental results show that the LazyRS-aware FTL can efficiently improve the write throughput and reliability of flash-based storage systems by up to 2.6 times and 31.2%, respectively.

STT-RAM (Spin-Transfer Torque Random Access Memory) appears to be a viable alternative to SRAM-based on-chip caches. Due to its high density and low leakage power, STT-RAM can be used to build massive capacity last-level caches (LLC). Unfortunately, STT-RAM has a much longer write latency and a much greater write energy than SRAM. Researchers developed hybrid caches made up of SRAM and STT-RAM regions to cope with these challenges. In order to store as many write-intensive blocks in the SRAM region as possible in hybrid caches, an intelligent block placement policy is essential. This paper proposes an adaptive block placement framework for hybrid caches that incorporates metadata embedding (ADAM). When a cache block is evicted from the LLC, ADAM embeds metadata (i.e., write intensity) into the block. Metadata embedded in the cache block are then extracted and used to determine the block’s write intensity when it is fetched from main memory. Our research demonstrates that ADAM can enhance performance by 26% (on average) when compared to a baseline block placement scheme.