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In this paper, an algorithm that provides absolute and proportional differentiation of packet delays is proposed with the objective of enhancing quality of service in future packet networks. It features an adaptive scheme that adjusts the target delay for every time slot to compensate the deviation from the target delay, which is caused by prediction error on the traffic to arrive at the next time slot. It predicts the traffic to arrive at the beginning of a time slot and measures the actual arrived traffic at the end of the time slot. The difference between them is utilized by the delay control operation for the next time slot to offset it. Because the proposed algorithm compensates the prediction error continuously, it shows superior adaptability to bursty traffic and exponential traffic. Through simulations we demonstrate that the algorithm meets the quantitative delay bounds and is robust to traffic fluctuation in comparison with the conventional non‐adaptive mechanism. The algorithm is implemented with VHDL on a Xilinx Spartan XC3S1500 FPGA, and the performance is verified under the test board based on the XPC860P CPU.

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