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The co fabrication of S ET & CMOS technology has already proved its ability to bring a drastic change in the era of nanodimensional devices. In our present work a well known combinational circuit, octal to binary encoder is demonstrated using hybrid S ET-CMOS technology in 22 nanometer node. We have presented power analysis for the circuit here. Power delay product for the circuit has also been done and a comparison is made with the conventional CMOS based circuit. S imulations are done using TCAD with the help of MIB model and BS IM4.6.1 model to establish the feasibility of the proposed model in case of room temperature operation.