The class of low-density parity-check (LDPC) codes is attractive, since such codes can be decoded using practical message-passing algorithms, and their performance is known to approach the Shannon limits for suitably large block lengths. For the intermediate block lengths relevant in applications, however, many LDPC codes exhibit a so-called "error floor," corresponding to a significant flattening in the curve that relates signal-to-noise ratio (SNR) to the bit-error rate (BER) level. Previous work has linked this behavior to combinatorial substructures within the Tanner graph associated with an LDPC code, known as (fully) absorbing sets. These fully absorbing sets correspond to a particular type of near-codewords or trapping sets that are stable under bit-flipping operations, and exert the dominant effect on the low BER behavior of structured LDPC codes. This paper provides a detailed theoretical analysis of these (fully) absorbing sets for the class of Cp; array-based LDPC codes, including the characterization of all minimal (fully) absorbing sets for the array-based LDPC codes for = 2; 3; 4, and moreover, it provides the development of techniques to enumerate them exactly. Theoretical results of this type provide a foundation for predicting and extrapolating the error floor behavior of LDPC codes. Index Terms-Absorbing set, bit-flipping, error floor, low-density parity-check (LDPC) codes, message passing decoding, nearcodeword, trapping set. I. INTRODUCTION L OW-density parity-check (LDPC) codes are a class of error-correcting codes based on sparse graphs. Their chief appeal is their excellent performance under practical decoding algorithms based on message passing, especially for

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Abstract-Many classes of high-performance low-density parity-check (LDPC) codes are based on parity check matrices composed of permutation submatrices. We describe the design of a parallel-serial decoder architecture that can be used to map any LDPC code with such a structure to a hardware emulation platform. High-throughput emulation allows for the exploration of the low bit-error rate (BER) region and provides statistics of the error traces, which illuminate the causes of the error floors of the (2048, 1723) Reed-Solomon based LDPC (RS-LDPC) code and the (2209, 1978) array-based LDPC code. Two classes of error events are observed: oscillatory behavior and convergence to a class of non-codewords, termed absorbing sets. The influence of absorbing sets can be exacerbated by message quantization and decoder implementation. In particular, quantization and the log-tanh function approximation in sum-product decoders strongly affect which absorbing sets dominate in the errorfloor region. We show that conventional sum-product decoder implementations of the (2209, 1978) array-based LDPC code allow low-weight absorbing sets to have a strong effect, and, as a result, elevate the error floor. Dually-quantized sum-product decoders and approximate sum-product decoders alleviate the effects of low-weight absorbing sets, thereby lowering the error floor.Index Terms-Low-density parity-check (LDPC) code, message-passing decoding, iterative decoder implementation, error floor, absorbing set.

This paper presents a power-and area-efficient 24-way time-interleaved SAR ADC designed in 65nm CMOS. At 2.8GS/s sampling rate the ADC consumes 44.6mW of power from a 1.2V supply while achieving peak SNDR of 50.9dB and retaining SNDR higher than 48.2dB across the entire first Nyquist zone. Introduction High demand for low-power ADCs with sampling frequencies of 2-3GHz and effective resolution of 7-8 bits is driven by applications such as direct-sampling receivers in cable modems [1] and digital baseband implementations of 60GHz communication systems [2]. The state-of-the-art solution [1] consumes 0.48W of power and occupies an active area of 5.1mm 2 . In this work both the area and power consumption of the ADC are each reduced by an order of magnitude. The main enabling technique for this improvement is miniaturization of the capacitors in the capacitive DAC of the interleaved SAR ADCs to the point where the ADC operates in a thermal noise limited regime. The minimum employed capacitor size is 50aF, ten times lower than previously reported [3] and well below the matching requirements, for a total sampling capacitance of 50fF and quantization noise at 10-bit level. This leads to a small area per channel and consequently allows for the distribution of input, clock, and reference signals without the need for power-hungry buffering. To be able to digitally correct static nonlinearities due to capacitor mismatches, a reduced radix of 1.85 is used in the capacitive DACs. A background least-mean-square (LMS) calibration technique that corrects static nonlinearities, offset, gain and timing mismatches has been implemented on the chip. Chip Architecture A high-level block diagram of the implemented ADC is shown in Fig. 1. It consists of M=24 time-interleaved channels, with two additional channels used for calibration. Each channel is split in two parts: analog (SARx_A, which also includes SAR logic), and digital (SARx_D). The digital part forms the final output by summing the weighted output bits from the analog part and the digital representation of the channel offsets. The values of digital weight coefficients and offsets are adaptive and are iteratively calculated in the 'linearity LMS' block. The timing LMS calculates timing mismatches and tunes the delay elements, Δt.Two modes of conversion, named the direct and the reverse switching, can be selected in all channels. In the direct switching mode, after sampling the input signal onto all capacitors in the DAC, the MSB capacitor is connected to the positive reference V rp , while all other capacitors are connected to the negative reference V rn as shown in Fig. 2.a. In the reverse switching, the MSB capacitor is connected to V rn and all others to V rp (Fig. 2.c). After the first bit is resolved, the MSB capacitor is connected to V rp if the resolved bit is '1' or to V rn if the resolved bit is '0', both in direct and reverse switching (Fig. 2.b and 2.d). All other bits are resolved in a similar way. These two modes of operation have transfer characteristics t...

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