Over the past several years, the adoption of HealthCare Monitoring Systems (HCS) in health centers and organizations like hospitals or eldery homes growth significantly. The adoption of such systems is revolutionized by a propelling advancements in IoT and Blockchain technologies. Owing to technological advancement in IoT sensors market, innovations in HCS to monitor patients health status have motivated many countries to strength their efforts to support their citizens with such care delivery systems under the directives of a physician who has access to patient’s data. Nevertheless, secure data sharing is a principal patient’s concern to be comfort to use such systems. Current HCS are not able to provide reassuring security policies. For that, one of our focus in this work, is to provide security countermeasures, likewise cost-efficient solution for HCS by integrating storage model based on Blockchain and Interplanetary File Systems (IPFS). Blockchain technology is an emerging solution in pharmaceutical industry and starts to take place for HCS and allows HealthCare providers to track connected devices and control access to shared data, hence protecting patients’ privacy. Furthermore, the addition of Edge and Fog computing has improved HCS to react in real-time and enhance their reliability. A variety of communication protocols can connect sensor devices to edge/Fog layer and the best choice will depend upon connectivity requirements: range, bandwidth, power, interoperability, security, and reliability. Instead, systems efficiency would decline and hurt if communication protocol is inconsistent. LoRa (Long Range) communications technology is emerging as the leader among Low-Power Wide-Area Networks (LPWANs) entering the IoT domain benefiting from many features such as long-range distances and low power consumption. This work proposes LoRaChainCare, an architecture model for HCS which combines the technologies Blockchain, Fog/Edge computing, and the LoRa communication protocol. A real implementation of LoRaChainCare system is presented and evaluated in terms of cost, run time and power consumption.

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Multi-Processor Systems on Chip (MPSoCs) have been proposed as a promising solution for the increasing demand of computational power required for recent application. The parallelization through SIMD (single instruction/multiple data) architectures has been a proven solution to speed up the processing of the recent application that exhibit massive amounts of data parallelism. The level of parallelism impacts the SIMD architecture performance and it is closely related to the design of the processing element. In this context this paper presents a new design methodology of designing processing element for SIMD architecture. The scope of this work is to reduce the pipeline stages of the soft-core processor to reduce the size of the PEs and so that to built up a high level parallelism architecture.I.

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