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A 32-Bit floating point signal processor IC is integrated with eight 16K x 4 bit SRAh4 chips on a silicon substrate, thus minimizing the parasitic loading to the processor buffer and enabling zero-waitstate access of the full 64K-bytes of memory. The module is rated at 25 MHz up to 125'C and 70 MHz at liquid nitrogen temperature. The assembly is packaged in a standard 133 pin PGA ceramic package identical in size and footprint with the package used for the signal processor IC alone. This multi-chip packaging approach has significant potential for improving system performance and reducing cost. The signal processing module described in this paper was designed as a vehicle for such demonstration. The electrical analysis and design criteria, the physical packaging, and testing strategies are discussed.

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