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Wide band gap semiconductor GaN has been shown during the past few years to be a very useful material for developing short-wavelength optoelectronic devices. Recently, AlGaNlGaN heterostructures have been an area of active research, owing to the demonstration of high power, high frequency electronic devices. ZDEG, formed at the interface of heterosmctures, has a high electron mobility. It is known that mobility and drain current are decreased by interface traps.In this paper, we study defects in AlGaNlGaN heteroshuctures using DLTS. The AlGaNlGaN heterostructures used in this study were grown by rf-plasma assisted molecular beam epitaxy(PA-MBE) on sapphire substrates. The AI mole fraction was kept at 0.2 for all the AlGaN layers.Fint of all, we checked current-voltage(1-V) at room temperature. Schonky barrier diodes(SBDs) with small leakage current were chosen for the capacitance-voltage(C-V) measurements. C-V data indicate confined electrons are located at 48nm h m top of GaN layers. DLTS was measured as a function of offset voltage. Figure 1 shows the DLTS spectra. The rate window was 18.28s.'. Two electron traps, labeled as DI, 02, are clearly observed at low temperatures. D2 peak is more dominant with increasing offset voltage. These data indicate that D2 t a p is located deeper than D1. It's included at the heterostructures interface.The Arrhenius plots of h(e,JT2) versus 1OOO/T for the major traps observed in AIGaNlGaN heterostructure are shown in the inset offigure 1 .The DLTS was measured by charging the fill pulse time in order study the origin of the traps. Figure 2, indicates that D2 can be peak amibuted to dislocations in heteroepitaxial AlGaNlGaN which displayed the logarithmic capture kinetics, extended dependence on fill pulse time, and broadened DLTS features expected for dislocation related traps.' We observed that D2 peak was decreased by annealing. As is shown in the figure 3, D2 peak was decreased remarkably at annealing temperature 900°CIn conclusion, two electron traps were detected. The trap levels are Ec-O.15eV and Ec-0.25eV, respectively. We believe that these traps are attributed to point defects and dislocations through analysing DLTS features measured fill pulse time. The trap related to the dislocation was reduced by annealing. Reference[I] B. Chattejee and S. A. Ringel, 1. Appl. Phys. 77,3885 (1995) 0-7803-7581 -5/02/$17.00 @ZOO2 IEEE 189