This paper presents an on-chip BiST technique for a common class of RF communication circuits, which has no measurable impact on the performance of the circuit-undertest. The technique is extremely robust and does not require the use of any DSP cores or off-line processing. The resultant architecture has very low overheads (<4% area overhead), ultra fast test times (30µs) and can simply be "plugged" into the RF circuit without the need for any co-design. We present the methodology along with associated circuitry and demonstrate its utility in the self-test of a standard cascode LNA.