This paper analyses the evolution of late and beyond CMOS technologies showing the relevant effect on the electronic design methods and rules due to the dramatic reduction of quality of the manufactured components. The paper argues that the main impact on such future technologies will be caused by the increase of the manufacturing defect ratio of components and circuits, the reduction of reliability through a huge increase of the error ratio and a drastic drop of the components quality. Consequently, new strategies of design have to be considered, among them the hierarchical fault tolerance that is presented in the paper. This fact will have implications in the design rules as we know them today.