Abstract-A complete review of the data vortex optical packet switched (OPS) interconnection network architecture is presented. The distributed multistage network topology is based on a banyan structure and incorporates a deflection routing scheme ideally suited for implementation with optical components. An implemented 12-port system prototype employs broadband semiconductor optical amplifier switching nodes and is capable of successfully routing multichannel wavelength-division multiplexing packets while maintaining practically error-free signal integrity (BER 10 12 ) with median latencies of 110 ns. Packet contentions are resolved without the use of optical buffers via a distributed deflection routing control scheme. The entire payload path in the optical domain exhibits a capacity of nearly 1 Tb/s. Further experimental measurements investigate the OPS interconnection network's flexibility and robustness in terms of optical power dynamic range and network timing. Subsequent experimental investigations support the physical layer scalability of the implemented architecture and serve to substantiate the merits of the data vortex OPS network architectural paradigm. Finally, modified design considerations that aim to increase the network throughput and device-level performance are presented.Index Terms-Interconnection networks (multiprocessor), optical interconnections, packet switching, photonic switching systems, wavelength-division multiplexing.

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Abstract-Wavelength-striped optical packet multicasting comprises a potentially important functionality for future energy-efficient network applications. We report on two multicast-capable architectures to experimentally demonstrate multiwavelength packet multicasting in an optical switching fabric testbed. The first design uses programmable packet-splitter-and-delivery that simultaneously supports the nonblocking unicast, multicast, and broadcast of high-bandwidth optical packets with parallel switches. This realization achieves the error-free multicasting of optical messages with 8 10 Gb/s payloads, with confirmed bit-error rates less than , and scalability of per-channel data rates to 40 Gb/s. We then introduce a second multistage multicasting architecture with lower hardware and energy costs, with the design trade-off of more complex routing logic; the experimental demonstration shows the successful switching and error-free multicasting of 8 10 Gb/s optical packets. The energy costs in terms of the capital and operational expenditures are then compared for the two designs, showing the benefits of the second multicast architecture.Index Terms-Future internet, multicast networks, optical communication, photonic switching systems, routing, wavelength-division multiplexing (WDM).

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Abstract-Future data centers will require novel, scalable memory architectures capable of sustaining high bandwidths while still achieving low memory access latencies. Electronic interconnects cannot meet the challenges presented by the need for multi-terabit off-chip memory data paths. In this work, the electronic bus between main memory and its host processor is replaced with a circuit-switched optical interconnection network. We investigate the impact of our optically connected memory system on large-scale architectures and experimentally validate the protocol using field-programmable gate array based processor nodes and a custom-designed memory controller. The processor communicates all-optically with multiple synchronous dynamic random access memory nodes using 4×2.5-Gb/s wavelength-striped payloads, operating error free with bit-error rates less than 10 −12 .