This brief presents a 10-bit 100-MS/s 1.2-V dualchannel pipelined CMOS analog-to-digital converter (ADC). The nine dual-channel pipelined stages share the operational amplifiers (op-amps) to optimize power and area. The proposed dynamic memory effect cancellation technique reduces the cross coupling caused by the residual charge in the op-amp sharing topology. The op-amp gain requirement of the dual-channel sample-and-hold circuit is also relaxed by the proposed memory effect cancellation technique. The prototype ADC achieves a peak signal-to-noise and distortion ratio of 56 dB for a 1-MHz input signal and a peak cross-coupling ratio of 67.4 dB at 100 MS/s while consuming 16.2 mW/channel from a 1.2-V supply. The prototype ADC occupies 1.96 mm 2 using a 0.13-μm CMOS technology. Index Terms-Dual channel, memory effect cancellation, op-amp sharing, pipelined analog-to-digital converter (ADC).

A switched-capacitor single-stage sigma-delta ADC with a fifth-order modulator is proposed. The proposed sigmadelta ADC employs feed-forward architecture with oversampling ratio (OSR) of 8. The modulator input signal range is extended beyond the full scale of the quantizer with proper coefficients scaling and internal DAC reference scaling. A 19-level quantizer with data weighted averaging dynamic element matching (DWA DEM) technique is employed to improve the linearity of a multi-bit DAC. The prototype ADC fabricated in a 0.13-μm CMOS technology achieves 63.7 dB SNDR with 1 MHz input signal over 6.25 MHz signal bandwidth while consuming 52.5 mW with the clock frequency of 100 MHz.

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