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a low-power register file is designed by using a low-swing strategy and modified NAND address decoders. The proposed low-swing strategy is based on the feedback scheme and uses dynamic logic to reduce the active feedback power. This method contains two parts: WRITE and READ strategy. In the WRITE low-swing scheme, the modified memory cell is used to support low-swing WRITE. The modified NAND decoder not only dissipates less power, but also enables a great deal of area reduction. Compared with the conventional single-ended register file, the low-swing strategy saves 34.5% and 51.15% bit-line power in WRITE and READ separately. The post simulation results indicate a 39.4% power improvement when the twelve ports are all busy.

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