A quadratic residue search method has previously been suggested to avoid the clustering usually encountered when hash address collisions occur and linear search methods are used. The search size, because of the property of quadratic residues, is limited to one half of the storage table. It is shown that for some classes of prime numbers the complement of the set of quadratic residues can easily be determined and hence the entire table of size p, where p is that prime number, can be searched.The principles of address calculation and merging are combined to yield an efficient sorting technique. Detailed flowcharts of the most important program steps are included. The characteristics of the proposed sort are discussed.

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In this paper we present a novel approach to delay-testing of VLSl logic chips based on the level-sensitive scan design (LSSD) methodology. The objective of the delay test is to reduce significantly the failures of multi-chip modules at system integration test while minimizing the complexity and cost of subassembly testing. Because system timing data are used to derive test specifications, the delay defects that are most likely to cause a system path failure are detected a high percentage of the time. With the implementation of the delay test in the wafer production line, the system final-test failure rate of multi-chip modules used in IBM mainframe machines has dropped significantly.

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