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An 8 b 700 MS/s 1 b/cycle asynchronous successive approximation register (SAR) analog to digital converter (ADC) which skips comparator metastability is presented. A delay-shift technique is proposed to shift the delay of comparator to generate a 1.5 b redundancy range and to accelerate comparison speed. This reduces the settling requirement and compensates for the dynamic offset by redundancy. The prototype ADC in 40 nm CMOS technology achieves an SNDR of 43.9 dB at Nyquist rate and consumes 5 mW with a 1.2 V supply. This results in an FoM of 56 fJ/conversion-step. Due to no extra calibration circuit, the core circuit occupies an area of only 0.006 mm 2 .