A simple design formula of a directional coupler that consists of two microstrip lines coupled through two narrow rectangular slots in a common ground plane is presented. By applying the design equations for the quasilumped quadrature coupler, the relative position and dimensions of the two narrow slots in the common ground plane can easily be determined. Typical designs have been implemented, and the S‐parameters for such a slot‐coupled directional coupler are measured and verified by simulated results. © 1998 John Wiley & Sons, Inc. Microwave Opt Technol Lett 17: 325–328, 1998.

A new method for time interval measurement is described. It consists of an externally triggered triangular waveform generator together with an analogue-to-digital converter to form a time-to-amplitude conversion chain (TACC). It features high resolution, large measurement range, improved linearity and simplicity: only one amplitude-to-time conversion and concise calculation.

Utilizing the propagation delay in a chain of logic elements to digitize short time intervals has a high potential in various applications because the method has an ultrashort measurement “dead time” and its complete timing circuit can be easily integrated in a single semiconductor chip. However, the existing single-lined chain suffers from serious nonlinearity due to the longer path lengths at the foldings which are unavoidable when the number of delay elements is large as high time resolution requires. We propose a new configuration in which the delay chain is branched. The delay elements of each branch evenly subdivide the corresponding larger folding path so all units have the same delay time. The proposed time-to-digital converter with an 81-delay-unit branched chain and a built-in calibration circuit has been implemented on a commercial programmable logic device. It is used to interpolate different time durations within the 100 ns period of a standard 10 MHz clock. The digital time deviates less than 0.3 ns throughout the entire range. A similar single-lined delay chain, constructed for comparison, exhibits timing error up to 32.7 ns. A major improvement in linearity has been achieved by our device.

No abstract