SIS i.s nii i i i t e r a c t i r~c tool for syiithcsis arid o p t i i i i c atioii of .scquciitial circiiits. (,'iiscii n sfntc t m i i s i t i o i i ta-1116 or a logic-lsuel drscriptiori of a scqurirtinl circuit, it produces (in optiini,-rd i i c t -l i s t i i i t h e target trchiiology roh ilr p rest ruing t h 6 .sf q iif 71 t i nl i rip ut -o ut y ut be li n ('io r. M a n y di,ffe re 71 t progrci iii .E n ii d nlgorith ins h a ut bet= ii i iitryrated into SIS, allouiiig t h e uscr to choost a i i i o i i y n unriety of trchiiiqncs (it each stage of t h c proctss. It is built 011 top of ~I I S I I [:?I a n d iiicliidt=s all ( c o i i i b i i i n - tioiial) optiiiiizatzon fechiriques t h e r e i n as w f l l as inaiiy eiihaiicemerits. SIS s e r i i m ( i s both a franrework ruithziiii~hich iurious algorithrirs c a n br trsttd arid compared. arid as a t o o l for autonicttic ,syiifhcsis a n d optinii-ntioir of seqiieiitinl carcu2t.s. This paper provides a n o i i c r i l i e~ of SIS: i n p u t specificntiori. STC; (sfate traiisztioii g r a p h ) i n n nip ul at 2 o n , a n d 11 t i~l logic opt ini c a t i o 71 n n d ut= rificat i o ii alg o rith rn s.

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Timing model extractor builds a timing model of a digital circuit for use with a static timing analyzer. This paper proposes a novel method of generating a gray box timing model from gate-level netlist by reducing a timing graph. Previous methods of generating timing models sacrificed accuracy and/or did not scale well with design size. The proposed method is simple, yet it provides model accuracy including arbitrary levels of latch time borrowing and capability to support timing constraints that span multiple blocks. Also, cpu and memory resources required to generate the model scale well with size of the circuit. The generated model can provide a capacity improvement in timing verification by more than two orders of magnitude.

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