Absfroct-An 8-bit, 200-megasample/second (Ms/s) flash converter with 400-MHz analog bandwidth and new error correction circuitry is described. A unique cascoded input stage and a dense bipdar process make the wide bandwidth possible. Three different strategies are employed to reduce errors arising from high input slew rate and comparator metastability.

A major limitation of multistage or pipeline ADC architectures is the need for a gain element between stages when the overall resolution exceeds about 9b. This gain element amplifies the residue of the first-stage conversion to a level that can be digitized by subsequent stages. The accuracy and settling requirements for this interstage amplifier dictates large gainbandwidth and leads to large power consumption. The architecture described here uses two residue signais to reduce amplifier requirements.

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