No abstract

This paper describes how offset calibration can be used to enhance the speed-resolution performance of ADCs while maintaining low levels of power dissipation. After selecting a high-speed ADC topology, we will justify the need for offset calibration and then present a brief overview of different ADC calibration topologies, indicating their relative merits and drawbacks. We will then describe in more detail how one-time foreground calibration was used to achieve a 0.18 µm CMOS, 1.8V, 1.6GS/s, 8b folding-interpolating ADC with 7.26 ENOB at Nyquist, which only dissipates 774 mW.