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Many very-high-complexity signal processing algorithms are required in future wireless systems, giving tremendous challenges to real-time implementations. In this paper, we present our industrial rapid prototyping experiences on 3G/4G wireless systems using advanced signal processing algorithms in MIMO-CDMA and MIMO-OFDM systems. Core system design issues are studied and advanced receiver algorithms suitable for implementation are proposed for synchronization, MIMO equalization, and detection. We then present VLSI-oriented complexity reduction schemes and demonstrate how to interact these high-complexity algorithms with an HLS-based methodology for extensive design space exploration. This is achieved by abstracting the main effort from hardware iterations to the algorithmic C/C++ fixed-point design. We also analyze the advantages and limitations of the methodology. Our industrial design experience demonstrates that it is possible to enable an extensive architectural analysis in a short-time frame using HLS methodology, which significantly shortens the time to market for wireless systems.

In this paper, we propose a novel multi-stage Parallel-ResidueCompensation (PRC) receiver architecture for enhanced suppression of the MAI in CDMA systems. We extract the commonality to avoid the direct Interference Cancellation and reduce the algorithm complexity from O(K 2 N) to O(KN). In the second part, scalable VLSI architectures are implemented in an FPGA prototyping system with an efficient Precision-C based System-on-Chip (SOC) design methodology. The design of SumSub-MUX Unit (SMU) combinational logic avoids the usage of dedicated multipliers with at least 10X saving in hardware resources. The most area/timing efficient design only uses area similar to the most area-constrained architecture but gives at least 4X speedup over a conventional design.

Abstract-A reduced complexity MIMO Kalman equalizer architecture is proposed in this brief by jointly considering the displacement structure and the block-Toeplitz structure. Numerical matrix-matrix multiplications with ( 3 ) complexity are eliminated by simple data loading process, where is the spreading factor. Finally, an iterative Conjugate-Gradient based algorithm is proposed to avoid the inverse of the Hermitian symmetric innovation covariance matrix in Kalman gain processor. The proposed architecture not only reduces the numerical complexity from ( 2 ) to ( log 2 ) per chip, but also facilitates the parallel and pipelined VLSI implementation in real-time processing.Index Terms-Displacement, Kalman, multiple-input-multipleoutput (MIMO), parallel architecture.