A variable-rate IF-sampled QAM receiver integrated circuit operates at symbol rates from 1 to 7MBaud in 4, 16, 32, 64, 128, 256, and 1024-QAM. The QAMreceiveris amonolithicmixed-signal device implemented in a 0.5pm triple-level metal single-poly CMOS process. Thedeviceincorporates a lObA/Dconverter, analogPLLs, interpolating demodulator, square-root raised cosine receive filters, timingkarrierrecovery loops, 20-tap complex equalizer, and a ReedSolomon forward error correction (FECI decoder that is compliant with European digitalvideo broadcasting (DVB) and Digital AudioVisual Council (DAVIC) standards [l]. Applications of this QAM receiver include digital cable-TV set-top terminals, cable modems, and digital microwave radios.A top level functional block diagram of the QAM receiver including an RF front-end is illustrated in Figurel. The integrated 10b A/D converter of the QAM receiver accepts a 2 V differential input up to 32MHz sampling rate. The digitized 18, centered data stream from the MD converter is demodulated to baseband in-phase (I) and quadrature (Q) channels by downmixing with cos(~cd2) and sin (nd2) [a]. The A/D converter is clocked by a crystal referenced integrated PLL at a fixed rate incommensurate with the symbol rate of the receiver. The reconstruction and symbol timing recovery uses a polynomial interpolator 131 Given two successive input samples using a canonic signed d i p t (CSD) architecture [21 duced by the RF tuner. The phase discriminant is filtered by an integral-plus-proportional lgop filter where the output drives a quadrature direct digital frequency spthesizer (QDDFS) 141. e phase derotator loop The complex equalizer consists of two transpose-form adaptive FIR filters -an 8-tap feedforward (FFE) filter and a 12-tap decision feedback (DFE) filter. Each filter emplqys q parallel-tap architecture that allows simple cqntrol distribution and dqta , as well as convenient scalability for ifferent equalizer spans (Figure 2). TheThe fundamental computational core of performs one copplex multiply-qpcumulate operation plus one corppleg coefficient update per symbol period qaing a single multqlier and two adders tiThe FEC decoder consists of 4 blocks: frame synchronization, convolutional deinterleaving, Reed-Solomon (RS) error correction, and derandomization. The frame synchronization block recovers MPEG framed data streams as defined in the DVB and DAVIC specification. The programmable convolutional deinterleaver is compatible with the Ramsey type I11 approach. The interleaving depth, 1,isprogrammablefrom 1=1-12,204whereIdivides204.An on-chip FL4Mis provided for I=1-12 andcontrol is suppliedfor an offchip RAM for 1~1 2 .The RS decoder processes the t = 8(n,k) = (204,188) shortened RS code, defined by the generator polynomial g(x) = (x+aO)(x+al) ... (x+a15) and the primitive polynomial p(x) = x8+x4+x3+x2+1. Derandomization ofthe data streamis performed to undo the energy dispersal function inserted a t the encoder and is based on the generator l +~l~+ x~~.The QAM receiver is extensively tested...

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