Abstract

In this paper, low power and high speed 8×8 Bit Vedic Multiplier is presented. A Novel technique for digit multiplication is produced that is quite different from the conventional method of multiplication like Add and Shift [1]. This paper presents a systematic design methodology for fast and delay efficient Vedic Multiplier based on Vedic Mathematics [2]. The multiplier architecture based on the Vertical and Crosswise algorithm of Ancient Indian Vedic Mathematics. In this paper, general technique for N×N multiplication is proposed and implemented; this gives less delay for calculating the multiplication results for 8×8 Bit Vedic Multiplier. In this paper, less delay and high speed 8×8 Bit Vedic Multiplier is presented. The multiplier cell of the adder is designed by using Pass Transistor (n-transistor), ptransistor used as cross coupled devices. The 8×8 Bit Vedic Multiplier circuit has been simulated using Microwind 3.1 VLSI Layout CAD tools. Simulated results for proposed 8×8 bit Vedic Multiplier circuit shows a great reduction in delay for 0.18 μm.

This paper present a design of Fast Fourier Transform (FFT) processor for high speed DSP application like OFDM based communication systems such as digital audio and video broadcasting (DAB & DVB), asymmetric digital subscriber loop (ADSL), where the basic need of this type of application is high speed processing on data. We designed high speed FFT processor with pipelined architecture which is efficient in terms of latency, with using fastest processing elements. In FFT processing, there are number of complex multiplication & addition operation. Multipliers takes more time for calculation therefore it increases the delay of FFT processor, hence the performance of processing element depends mostly on multipliers. We have designed the processing element i.e. floating point multiplier using two different types of fixed point multipliers, CSA multiplier which is conventionally high speed multiplier & Vedic multiplier based on Vedic mathematics. We have done the comparative analysis of CSA multiplier & Vedic multiplier on Xilinx 13.1i with Spartan-6 device (xc6slx100t-4-fgg900). Using these we have designed radix-2 4 pipelined architecture FFT processor.