The Medipix2 chip is a pixel-detector readout chip consisting of 256 256 identical elements, each working in single photon counting mode for positive or negative input charge signals. Each pixel cell contains around 500 transistors and occupies a total surface area of 55 m 55 m. A 20-m wide octagonal opening connects the detector and the preamplifier input via bump bonding. The preamplifier feedback provides compensation for detector leakage current on a pixel by pixel basis. Two identical pulse height discriminators are used to create a pulse if the preamplifier output falls within a defined energy window. These digital pulses are then counted with a 13-b pseudorandom counter. The counter logic, based in a shift register, also behaves as the input-output register for the pixel. Each cell also has an 8-b configuration register which allows masking, test-enabling and 3-b individual threshold adjust for each discriminator. The chip can be configured in serial mode and readout either serially or in parallel. The chip is designed and manufactured in a 6-metal 0.25m CMOS technology. First measurements show an electronic pixel noise of 140 e root mean square (rms) and an unadjusted threshold variation around 360 e rms.

The Medipix2 chip is a pixel detector readout chip consisting of 256 x 256 identical elements, each working in single photon counting mode for positive or negative input charge signals. Each pixel cell contains around 500 transistors and occupies a total surface area of 55 Pm x 55 Pm. A 20 Pm width octagonal opening connects the detector and the preamplifier input via bump-bonding. The preamplifier feedback provides compensation for detector leakage current on a pixel by pixel basis. Two identical pulse height discriminators are used to create a pulse if the preamplifier output falls within a defined energy window. These digital pulses are then counted with a 13-bit pseudo-random counter. The counter logic, based in a shift register, also behaves as the input/output register for the pixel. Each cell also has an 8-bit configuration register which allows masking, test-enabling and 3-bit individual threshold adjust for each discriminator. The chip can be configured in serial mode and read out either serially or in parallel. The chip is designed and manufactured in a 6-metal 0.25 Pm CMOS technology. Preliminary measurements show very good agreement with simulations. 1484 0-7803-7324-3/02/$17.00 © 2002 IEEE

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