Massive-MIMO and beamforming techniques have long been proposed as a means of increasing cellular network capacity and improving signal to interference ratio performance. The implementation of such systems requires a large number of signal transmission paths. To realize this, a distributed array of power amplifiers (PAs) is likely to be needed. These PAs will possess similar, but unique, characteristics which will alter over time independently due to temperature drift and component ageing. In order to operate all PAs in both a linear and efficient fashion a linearisation technique, such as Digital Pre-Distortion (DPD), must be used. DPD algorithms benefit from reconfigurability, low latency and power efficiency, all traits associated with Field Programmable Gate Arrays (FPGAs). This demonstration shows how an FPGA, specifically a ZYNQ System on a Chip (SoC), can be used in tandem with a transceiver board, the FMCOMMS2, to implement a DPD system.

In modern radio frequency (RF) transceivers the power amplifier (PA) is a central component in terms of power consumption. Achieving efficient performance in this component results in the PA output signal becoming distorted. Linearisation can be performed using techniques such as Digital Pre-Distortion (DPD). The pre-distorter operation of a DPD system involves the constant computation of a distorted signal to ensure linear operation of the nonlinear power amplifier. In this work a novel polynomial evaluation scheme is proposed to optimise the pre-distorter operation within a DPD system. Improvements to latency and hardware requirements are possible with new techniques. Validation of the proposed design was conducted using FPGA implementations and compared to incumbent pipelined solutions for both low latency and hardware efficiency. The proposed method indicated hardware savings of 67.8%, while operating 58.7% faster, compared to an existing implementation.

Power amplifiers are widely employed electronic devices in various fields such as mobile networks and radio frequency (RF) transceivers. To achieve efficient operations, power amplifiers can often suffer from nonlinearity problems. This problem can be mitigated through the use of linearization techniques, such as digital predistortion, regarded as the most promising solution to power amplifier linearization. Behavioural modeling is a substantial part of the digital predistortion, responsible for acquiring the coefficients that are necessary to linearize the power amplifier. A Complex Reduced Non-Uniform Generalized Memory Polynomial model was proposed to reach comparable performance of accuracy as Memory Polynomial Model with reduced complexities. The proposed model was tested with a 5MHz LTE signal measured at the input and output of a Doherty PA under different conditions of nonlinearities, memory effects and attenuations as well as PA working powers. It can be observed that the proposed model shows superior accuracy at low complexities, when the PA has higher levels of nonlinearity and memory depth while still maintaining low complexities. Over 60% of coefficients reduction could be reached at the same level of accuracy compared to the MP model.

Behavioral models are intended as high level mathematical descriptions which require less computational effort to simulate behavior compared to physical or circuit level equivalent models. When designed and dimensioned properly they are well suited to concise characterization of power amplifiers under different operating conditions. In this paper we compare the relative performance of several behavioral models for modelling an asymmetric Doherty power amplifier for their use in distributed arrays.

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