Abstract-Verification is the most integral part of chip manufacturing and testing and is as important as the designing. Verification provides with the actual implementation and functionality of a Design under Test (DUT) and checks if it meets the specifications or not. In this paper, a communication protocol has been verified as per the design specifications. The environment so created completely wraps the design under verification and observes an optimum functional and assertion based coverage. The coverage so obtained is 100% assertion based coverage and 83.3% functional coverage using SV (SystemVerilog). The total coverage so obtained is 91.66%.
SystemVerilog is the emerging language of choice for modern day VLSI design and verification. SystemVerilog (SV) brings a advanced level of abstraction to the system being modeled. The advanced constructs it utilizes its OOP capability make it stand apart from other verification languages. In this paper we will be analyzing the performance of SV testbench over Verilog testbench, using well defined comparison parameters tested against an actual IP design block, along with other features of the SV language.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.