Many signal processing systems are synthesized to execute datadominated applications. Their behavior is described in a high-level programming language, where the code is typically organized in sequences of loop nests and the main data structures are multidimensional arrays. Since data transfer and storage have a significant impact on both the system performance and the major cost parameters -power consumption and chip area, the designer must spend a significant effort during the system development process on the exploration of the memory subsystem in order to achieve a cost-optimized design. This paper focuses on the reduction of the dynamic energy consumption in the hierarchical memory subsystem of multidimensional signal processing systems, starting from the high-level behavioral specification of the application. The paper presents an algorithm which identifies those parts of arrays from a high-level specification that are intensely accessed (for read and/or write operations), whose storage on-chip yields the highest benefit in terms of dynamic energy consumption. Tested on a twolayer memory hierarchy (scratch-pad and off-chip memories), this algorithm led to significant savings of energy in comparison to previous computation models.

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Many signal processing systems, particularly in the multimedia and telecom domains, are synthesized to execute data-dominated applications. Their behavior is described in a high-level programming language, where the code is typically organized in sequences of loop nests and the main data structures are multidimensional arrays. Since data transfer and storage have a significant impact on both the system performance and the major cost parameters-power consumption and chip area, the designer must spend a significant effort during the system development process on the exploration of the memory subsystem in order to achieve a cost-optimized design. This paper presents a memory allocation methodology for multidimensional signal processing applications, focusing on the problem of efficiently mapping the multidimensional signals from the algorithmic specification into the physical memory. In a first phase, two previous mapping models are implemented within a common theoretical framework, which is advantageous from both the point of view of computational efficiency and the amount of allocated data storage. Different from all the previous mapping models that aim to optimize the memory sharing between the elements of a same array (creating separate windows in the physical memory for distinct arrays), this proposed mapping model exploitin a second phase-the possibility of memory sharing between the elements of different arrays. As a consequence, this signal assignment approach yields significant savings in the amount of data storage resulted after mapping.