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High density and integrated packaging of electronic device requires fine pitch. This packaging causes reliability problem in electronic device. One of them, warpage of the package occurred at chip assembly process may affect reliability. Therefore, if the simulation at the time of a chip assembly process is possible, it will be able to evaluate warpage in advance. It is very effective for development of a new product. Then, in this paper, the build-up package is regarded as a single material and the simulation technique of accuracy warpage at the time of chip assembly is reported. Next it is investigated the simulation technique for package warpage at the chip assembly process. Finnaly, it analyzed about the properties which affect warpage.