No abstract

Factors such as expanding feature set and algorithmic designs drive modern SoCs towards larger and tightly coupled mixed signal content. Traditional digital HDLs and Verification oriented languages come forth to support this development by evolving with powerful mixed signal modeling facilities for early and improved verification of digitalanalog (and vice-versa) interaction. Under such circumstances, it becomes essential for the AMS verification engineer to figure out ways for overcoming continuous time modeling challenges in the traditionally event driven digital simulators. The paper intends to highlight the endeavors and optimizations for such an effort, uncovering the aforesaid modeling technology's sweet spots, bottlenecks and abstraction requirements. Optimizations are discussed for the bottlenecks discovered, prominently continuous time filters and feedback circuits, and elaborations are presented on new simulation concerns such as numerical instability. Results are presented reasserting that while such a modeling approach can present almost 100x speed enhancement, it can also result in a severe speed penalty when misapplied (200x slower, here).