We propose the use of a simple, cheap, and easy technique for the study of dynamic and synchronization of the coupled systems: effects of the magnetic coupling on the dynamics and of synchronization of two Colpitts oscillators (wireless interaction). We derive a smooth mathematical model to describe the dynamic system. The stability of the equilibrium states is investigated. The coupled system exhibits spectral characteristics such as chaos and hyperchaos in some parameter ranges of the coupling. The numerical exploration of the dynamics system reveals various bifurcations scenarios including period-doubling and interior crisis transitions to chaos. Moreover, various interesting dynamical phenomena such as transient chaos, coexistence of solution, and multistability (hysteresis) are observed when the magnetic coupling factor varies. Theoretical reasons for such phenomena are provided and experimentally confirmed with practical measurements in a wireless transfer.

The preamplifier module is a crucial element while designing dynamic latch comparators. The traditional double tail comparator utilizes a differential pair as the preamplifier stage. The circuit is generally suffered from high power dissipation and low comparison speed. This research reports the design and implementation of a low‐offset, low‐power and high‐speed dynamic latch comparator. In this work, an enhanced differential pair amplifier is employed in the preamplifier stage, to improve the power dissipation and the comparison speed of the device. A custom latch structure with rigorous transistor sizing was implemented to avoid short circuit current and mismatch in the module. The effective trans‐conductance of the cross‐coupled transistors of the latch was therefore improved for an optimal time delay solution. The equation associated with the delay was derived and the parameters that embody the speed were identified. The design has been validated by corner analysis and post‐layout simulation results in 65 nm CMOS technology process, which reveals that the proposed circuit can operate at a higher clock frequency of 20 GHz with a low‐offset of 4.45 mV and 14.28 ps propagation delay, while dissipating only 67.8 μW power consumption from 1 V supply and exhibited lowest PDP of 0.968 fJ. Moreover, the core circuit layout occupies only 183.3 μm2.

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