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SUMMARYThree novel CMOS realizations for the fully differential voltage second-generation inverting current conveyor (FDVCCII-) are proposed in this paper. The first realization has a limited input range, and the other two realizations have a rail to rail input range and show excellent features in linearity and bandwidth. As an application to the FDVCCII-, a floating gyrator is proposed. A floating inductor is realized using the floating gyrator and it is used in realizing a second-order low-pass filter, which is simulated and compared with the ideal result. All circuits are simulated with SPICE using CMOS 0.35 m technology and supply voltages ±1.5 V to verify the theoretical results.

This paper presents two new CMOS realizations for the inverting current conveyor (ICCII). The proposed realizations offer enhanced features compared to previously reported ICCII. Also new oscillator circuits based on using the ICCII as an active element are presented. The presented oscillator circuits have the advantage that both the oscillation frequency and the oscillation condition can be adjusted independently. Also another application to the ICCII, which is a floating inductor, is proposed. A second order low pass filter using the proposed floating inductor is simulated and compared with the ideal result. The proposed ICCIIs and the presented applications are tested with SPICE simulations using CMOS 0.35 lm technology to verify the theoretical results.

Abstract-This paper presents a sub-Nyquist rate data acquisition front-end based on compressive sensing theory. The front-end randomizes a sparse input signal by mixing it with pseudo-random number sequences, followed by analog-to-digital converter sampling at sub-Nyquist rate. The signal is then reconstructed using an L1-based optimization algorithm that exploits the signal sparsity to reconstruct the signal with high fidelity. The reconstruction is based on a priori signal model information, such as a multi-tone frequency-sparse model which matches the input signal frequency support. Wideband multi-tone test signals with 4% sparsity in 5~500 MHz band were used to experimentally verify the front-end performance. Single-tone and multi-tone tests show maximum signal to noise and distortion ratios of 40 dB and 30 dB, respectively, with an equivalent sampling rate of 1 GS/s. The analog front-end was fabricated in a 90 nm complementary metal-oxide-semiconductor process and consumes 55 mW. The front-end core occupies 0.93 mm .