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ADC-based receivers are currently being proposed in high-speed serial link applications to enable flexible, complex, and robust digital equalization in order to support operation over high loss channels [1][2][3]. However, the power dissipation of the ADC, as well as the digital equalization that follows, is a major concern for wireline receiver applications [3]. In this work, a hybrid ADC-based receiver architecture is presented that introduces innovations in both the ADC and the digital equalizer design. First, an analog 3-tap feed-forward equalizer (FFE) is efficiently embedded into a 6b time-interleaved SAR ADC, allowing for reductions in both ADC resolution and digital equalizer complexity. Second, significant power reduction is achieved by detecting reliable symbols at the ADC output and dynamically enabling/disabling the digital equalizer. Figure 3.6.1 shows PAM2 BER bathtub curves for two backplane channels with different attenuations. The low-loss channel has an open eye with a voltage region over which a two-level slicer can reliably detect both '0' and '1' symbols at the required BER. Increased ISI from the high-loss channel causes the received eye to close with a slicer threshold set at the nominally optimal zero level, where significant errors are observed. In this case, typical receivers employ equalization on all received symbols to reduce ISI and open the eye to achieve the target BER. Certain received signal levels, however, have a very low probability of generating an error for a given symbol and do not necessarily require additional equalization. Our hybrid ADC-based receiver takes advantage of this to save power by employing a three-level detector with programmable thresholds that allows for reliable detection of both '0' and '1' symbols when the received signal falls outside the ambiguous region, and dynamically disables the digital equalizer on a per-symbol basis. For symbols in the ambiguous region that cannot be reliably detected, the digital equalizer is dynamically enabled to further remove ISI and achieve the target BER. Combining this technique with embedded FFE in the ADC allows for a significant reduction in digital equalizer power. The embedded FFE reduces the percentage of symbols in the ambiguous region [4].The hybrid ADC-based receiver utilizes a 32-way time-interleaved 6b SAR ADC with embedded 3-tap FFE, as shown in Fig. 3.6.2. This 10GS/s converter has eight parallel sub-ADCs, each consisting of a front-end T/H clocked at 1.25GHz followed by four asynchronous unit SAR ADCs. A differential divide-by-four circuit is used with 5GHz complementary input clocks to generate the eight phases spaced at 100ps that clock the sub-ADC T/Hs. Digitally controlled capacitor banks, with a <0.4ps resolution and ~30ps range, are employed to calibrate timing mismatches in the clock distribution to the T/H blocks. The ADC includes calibration DACs for comparator offset, linear gain, and sampling clock skew. A switched-capacitor implementation allows for efficient embedding of the 3-tap FFE, which i...