High-K (HK) & Metal-Gate (MG) transistor technology have become a mainstream for the logic & SOC processes. On HK/MG process, bias-temp instability (BTI) poses continuous challenges on the technology scaling despite the reduced Vcc. In recent technologies, PMOS NBTI degradation is increased while NMOS PBTI was reduced with HK scaling.Interfacial Layer (IL) scaling underneath the HK that affects PMOS NBTI and device performance is very challenging. Impact of technology scaling on BTI and BTI on FinFET technology is discussed.

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