Power consumption is a limiting factor to FPGA viablility in applications such as portable devices. LUT-based Mask-Programmable Gate-Arrays (LUT-based MPGAs) are alternatives to reach the fast turnaround times of an FPGA with low design cost and low power consumption. A LUTbased MPGA preserves the same logic-structure of a LUTbased FPGA. Unlike FPGAs, the programmable configuration and interconnect is mask-programmable. This paper describes a methodology to estimate power consumption in a LUT-based MPGA. The proposed methodology uses a gate-power estimation tool. The dynamic and static power of the basic-gates are modeled in a library. The interconnect is easily modeled because the programmable metal-masks are predefined. A comparison with a transistor-level simulation shows an average difference of 20% with the final power result. The experiments show that the major contributor of the power consumption in the MPGA is the clock network. Power results on MPGAs and FPGAs are compared.We see that the dynamic power consumption in the logic is reduced by 73%. The major power reduction is observed in the interconnects. Static power consumption in the LUT-based MPGA is insignificant compared its dynamic power consumption.

Field-programmable gate-arrays (FPGAs) are used for application-specific standard product (ASIC) prototyping or small volume products. In medium to large volume products, the prototyping design or the small volume product is converted to another integrated circuit (IC) structure such as maskprogrammable gate arrays (MPGAs). MPGAs are of growing importance because of the increase of design cost, and turnaround times in ultra-deep submicron technologies which mostly impact ASICs. Several design methodologies have been proposed in recent years for converting an evaluated FPGA prototype-design into an MPGA. The MPGA design uses potentially less area, delay, and dynamic power consumption than the FPGA design.In a conversion from an FPGA design, the engineer looks for a simple flow to minimize time-to-market. It is well known that the most time consuming process in an IC design is verification. Formal verification checks the functionality of the designed circuit. Physical verification checks the timing (and in same cases the power consumption) of the designed circuit. Formal verification is simplified if the same gate-level netlist of the FPGA is used in the conversion. Simplification of physical verification is possible by exploiting the regularity in the IC layout.In this thesis, two new Look-Up Table-